View UPD31172_5356.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD31172
VRC4172 TM COMPANION CHIP FOR VR4121
TM
DESCRIPTION
The PD31172 (commercial name: VRC4172) is a companion chip designed for NEC's PD30121 microprocessor (commercial name: VR4121). The VRC4172 has the following functions available on chip: a USB host controller, an IEEE1284 parallel controller, a 16550 serial controller, a PS/2 controller, general-purpose ports (GPIO), programmable chip select (PCS), and a PWM controller (a duty modulated light pulse generation function for LCD backlighting). The VRC4172 can be directly connected to the VR4121, allowing a reduction in the man-hours required for development of a WindowsTM CE system. Detailed function descriptions are provided in the following user's manual. Be sure to read it before designing. * VRC4172 User's Manual (U14386E)
FEATURES
* Directly connectable to VR4121 * On-chip USB host controller * USB ports: 2 * Compliant with the USB OpenHCI specifications, release 1.0 * Communicates with USB device asynchronously with host CPU * Full-speed (12 Mbps) and low-speed (1.5 Mbps) modes supported * System clock: 48 MHz * On-chip PS/2 controller * On-chip IEEE1284 parallel controller * On-chip 16550 serial controller * General-purpose ports (GPIO): 24 * On-chip PWM controller * Duty modulated light pulse generation function for LCD backlighting * Internal maximum operating frequency: 48 MHz * Power supply voltage: VDD = 3.3 V 0.3 V * Package: 208-pin plastic FBGA
APPLICATIONS
* Battery-driven portable information devices * Peripheral devices for PCs, etc.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14388EJ2V0DS00 (2nd edition) Date Published May 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
PD31172
ORDERING INFORMATION
Part Number Package 208-pin plastic FBGA (15 x 15) Internal Maximum Operating Frequency 48 MHz
PD31172F1-48-FN
PIN CONFIGURATION
* 208-pin plastic FBGA (15 x 15)
PD31172F1-48-FN
Bottom View 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 UTRPNML K J HGFEDCBA
Top View
A BCDEFGH J K LMNPRTU Index mark
2
Data Sheet U14388EJ2V0DS00
PD31172
Symbol A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 GND AUTOFEED# PE INIT# IOCHRDY AD19 AD20 AD21 AD22 AD23 AD24 Reserved Reserved DP1 DN2 DP2 LCDRDY PS2CLK VDD VDD BUSY GND AD12 AD13 AD14 AD15 AD16 AD17 AD18 GND DN1 VDD GND WR# PS2DATA
Note 1
Name
Symbol C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 GND
Name
Symbol E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H14 H15 H16 H17 J1 J2 J3 J4 J14 CD3 CD7 GND
Name
Symbol J15 J16 J17 K1 K2 K3 K4 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 GND
Name
STROBE# ACK# ERROR# AD6 AD7 AD8 VDD AD9 AD10 AD11 LCDBAK SMI# USBINT# GND RD# GND SELECTIN# DIR1284 PS2INT SELECT AD0 AD1 AD2 GND AD3 AD4 AD5 VDD IEN WAKE OCI1 LCDCS# GPIO23 GPIO19
UUCAS# ROMCS3# GPIO14 GPIO10 GPIO7 GPIO3 EXCS3# EXCS0# SCAS# SRAS# GPIO13 GPIO9 GPIO6 GPIO2 EXCS4# EXCS1# Reserved (0) GND GPIO12 GPIO8 GPIO5 GPIO1 EXCS5# EXCS2# Reserved (0) CKE RESET BUSRQ0# GPIO4 GPIO0 GND DSR# RXD RI#
Note 2 Note 2
PPON1 OCI2 USBRST# GPIO22 GPIO18 CD2 CD6 SCLK PPON2 LCAS# MRAS0# GPIO21 GPIO17 CD1 CD5 Reserved Reserved UCAS# MRAS1# GPIO20 GPIO16 CD0 CD4 Reserved
Note 1 Note 1
Note 1
L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17
Note 1
ARBCLKSEL ULCAS# ROMCS2# GPIO15 GPIO11 VDD GND VDD
Notes 1. Either leave pins A12, A13, G14, G15, and H14 open, or input 0 V. 2. Always input 0 V to pins L16 and M16. Remark # indicates active low.
Data Sheet U14388EJ2V0DS00
3
PD31172
Symbol P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 Name HOLDRQ# BUSAK0# BUSRQ1# GND DATA31 DATA30 DATA29 DATA28 VDD DATA27 DATA26 DATA25 DATA24 CLKOUT48M DCD# TXD INTRP Symbol R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 Name HOLDAK# GND BUSAK1# DATA23 DATA22 VDD DATA21 DATA20 GND DATA19 DATA18 VDD DATA17 DATA16 CTS# GND XOUT48M Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 Name BUSCLK GND VDD VDD DATA15 DATA14 GND DATA13 DATA12 DATA11 DATA10 GND DATA9 DATA8 VDD VDD XIN48M Symbol U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Name IOCS16# IRQ IOR# IOW# GND DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DTR# RTS# GND
Remark
# indicates active low.
4
Data Sheet U14388EJ2V0DS00
PD31172
PIN IDENTIFICATION
ACK#: AD (0:24): ARBCLKSEL: AUTOFEED#: BUSAK (0:1)#: BUSCLK: BUSRQ (0:1)#: BUSY: CD (0:7): CKE: CLKOUT48M: CTS#: DATA (0:31): DCD#: DIR1284: DN (1:2): DP (1:2): DSR#: DTR#: ERROR#: EXCS (0:5)#: GND: GPIO (0:23): HOLDAK#: HOLDRQ#: IEN: INIT# INTRP: IOCHRDY: IOCS16#: IOR#: IOW#: IRQ: LCAS#: LCDBAK: LCDCS#: LCDRDY: Remark Acknowledge Address Bus Arbitration Clock Select Autofeed Bus Acknowledge System Bus Clock Bus Request Busy Centronics Data Clock Enable Clock Out of 48 MHz Clear to Send Data Bus Data Carrier Detect Direction of 1284 USB D- USB D+ Data Set Ready Data Terminal Ready Error External CS Ground General Purpose I/O Hold Acknowledge Hold Request USB Input Enable Initialize Interrupt I/O Channel Ready IO Chip Select 16 I/O Read I/O Write I/O Request Lower Column Address Strobe LCD Back Light LCD Chip Select LCD Ready VDD: WAKE: WR#: XIN48M: XOUT48M: USBINT#: USBRST#: UUCAS#: STROBE#: TXD: UCAS#: ULCAS#: SCLK: SELECT: SELECTIN#: SMI#: SRAS#: MRAS (0:1)#: OCI (1:2): PE: PPON (1:2): PS2CLK: PS2DATA: PS2INT: RD#: RESET: RI#: ROMCS (2:3)#: RTS#: RXD: SCAS#: DRAM Row Address Strobe Over Current Interrupt Paper End Port Power ON PS2 Clock PS2 Data PS2 Interrupt Read Reset Ring Indicator ROM Chip Select Request to Send Receive Data Column Address Strobe for SDRAM SDRAM Clock Select Select in USB System Interrupt Row Address Strobe for SDRAM Strobe Transmit Data Upper Column Address Strobe Lower Byte of Upper Column Address Strobe USB Interrupt USB Reset Upper Byte of Upper Column Address Strobe Power Supply Voltage Wake Up Interrupt Write Clock In of 48 MHz Clock Out of 48 MHz
# indicates active low.
Data Sheet U14388EJ2V0DS00
5
PD31172
INTERNAL BLOCK DIAGRAM AND EXTERNAL BLOCK CONNECTION EXAMPLE
VRC4172 48 MHz DRAM controller SDRAM PCI bus controller
Internal PCI bus
USB host controller (OpenHCI 1.0)
2 ports
IEEE1284 parallel controller
.... ....
VR4121
16550 serial controller
RS-232-C driver
System bus
PS/2 controller
PWM controller LCD backlight PCS (6 bits)
GPIO (24 bits)
PMU
ICU
6
Data Sheet U14388EJ2V0DS00
PD31172
CONTENTS
1.
PIN FUNCTIONS................................................................................................................................... 8
1.1 1.2 1.3 1.4 Pin Function List ....................................................................................................................................... 8 Special Status Pins ................................................................................................................................. 11 External Processing of Pins and Drive Capacity.................................................................................. 13 Recommended Connection of Unused Pins......................................................................................... 15
2. 3. 4.
ELECTRICAL SPECIFICATIONS...................................................................................................... 16 PACKAGE DRAWING ....................................................................................................................... 38 RECOMMENDED SOLDERING CONDITIONS................................................................................ 39
Data Sheet U14388EJ2V0DS00
7
PD31172
1. PIN FUNCTIONS 1.1 Pin Function List
(1) System bus interface signals
Signal Name SCLK AD (0:24) DATA (0:31) LCDCS# RD# I/O I/O I/O I/O Input I/O This is the SDRAM operating clock. These form a 25-bit address bus. These form a 32-bit data bus. This is the LCD chip select signal. This signal becomes active when the VR4121 accesses the LCD using the AD or data bus. * Output: This signal becomes active when the VRC4172 accesses SDRAM. * Input: WR# I/O This signal becomes active when the VR4121 reads data from the VRC4172's PCI host bridge. Function
* Output: This signal becomes active when the VRC4172 writes data to SDRAM. * Input: This signal becomes active when the VR4121 writes data to the VRC4172's PCI host bridge.
LCDRDY ROMCS (2:3)# CKE UUCAS# ULCAS# MRAS (0:1)# UCAS# LCAS# IOR# IOW# RESET IOCS16# IOCHRDY HOLDRQ# HOLDAK# SRAS# SCAS# BUSRQ (0:1)# BUSAK (0:1)# INTRP IRQ USBINT# PS2INT BUSCLK ARBCLKSEL
Output I/O I/O I/O I/O I/O I/O I/O Input Input Input Output Output Output Input I/O I/O Input Output Output Output Output Output Input Input
This is the LCD ready signal. This signal becomes active when a state is entered whereby the VRC4172 can acknowledge an access to the LCD area from the VR4121. This is an SDRAM chip select signal. This is the SDRAM clock enable signal. This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (24:31) pins. This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (16:23) pins. This is an SDRAM chip select signal. This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (8:15) pins. This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (0:7) pins. This is the system bus I/O read signal. This signal becomes active when any resource except the USB inside the VRC4172 is accessed. This is the system bus I/O write signal. This signal becomes active when any resource except the USB inside the VRC4172 is accessed. This is the system bus reset signal. This is the dynamic bus-sizing request signal. This is the system bus ready signal. This is the system bus access right request signal. This is the system bus access enable signal. This is the SDRAM RAS signal. This is the SDRAM CAS signal. This is a signal input from the external bus master requesting access to the system bus. This is a signal output to the external bus master permitting access to the system bus. This is an interrupt request signal from the 16550 serial controller or the IEEE1284 parallel controller. This is an interrupt request signal from the general-purpose ports (GPIO (0:23)) or the IEEE1284 parallel controller. This is an interrupt request signal from the USB host controller. This is an interrupt request signal from the PS/2 controller. This is the system bus clock. This is a clock select signal for arbitrating the system bus (controls the HOLDRQ# signal) (1: Internal clock used, 0: BUSCLK used)
8
Data Sheet U14388EJ2V0DS00
PD31172
(2) USB Interface Signals
Signal Name DP (1:2) DN (1:2) PPON (1:2) OCI (1:2) IEN WAKE SMI# USBRST# I/O I/O I/O Output Input Input Output Output Input This is the positive data signal. This is the negative data signal. This is the USB route-hub-port power supply control signal. This is the USB route-hub-port over-current status signal. Make this signal active when the current flowing through the Vbus line of the USB exceeds the reference value. This is the USB buffer input enable signal. Make this signal active when the input signal to the USB port is validated. This is a wakeup interrupt request signal. This is a system interrupt request signal. This is the reset signal for the USB clock. Function
(3) IEEE1284 Interface Signals
Signal Name CD (0:7) STROBE# ACK# BUSY PE SELECT AUTOFEED# SLECTIN# ERROR# INIT# DIR1284 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output These are data signals This is the data strobe signal. This is the acknowledge signal. This is the busy signal. This is the paper-end signal. This is the select signal. This is the autofeed signal. This is the select input signal. This is the fault signal. This is the initialization signal. This signal outputs the transfer direction status. Function
(4) RS-232-C Interface Signals
Signal Name RXD CTS# DSR# TXD RTS# DTR# DCD# RI# I/O Input Input Input Output Output Output Input Input This is the receive data signal. This is the transmit enable signal. This is the data set ready signal. This is the transmit data signal. This is the transmit request signal. This is the terminal equipment ready signal. This is the carrier detection signal. This is the call display signal. Function
Data Sheet U14388EJ2V0DS00
9
PD31172
(5) PS/2 Interface Signals
Signal Name PS2CLK PS2DATA I/O I/O I/O This is the PS/2 clock signal. This is the PS/2 data signal. Function
(6) General-Purpose Port Signals
Signal Name GPIO (0:23) I/O I/O These are general-purpose I/O signals. Function
(7) General-Purpose Chip Select Signals
Signal Name EXCS (0:5)# I/O Output Function These are general-purpose chip select signals.
(8) LCD Interface Signals
Signal Name LCDBAK I/O Output Function These are signals for controlling the LCD backlighting.
(9) Clock Signals
Signal Name XIN48M XOUT48M CLKOUT48M I/O Input Output Output Function This is the 48 MHz oscillator input pin. Connect to one side of a crystal resonator. This is the 48 MHz oscillator output pin. Connect to the other side of the crystal resonator. This is the 48 MHz clock output for the FIR of the VR4121.
10
Data Sheet U14388EJ2V0DS00
PD31172
1.2 Special Status Pins (1/2)
Signal Name SCLK AD (0:24) DATA (0:31) LCDCS# RD# WR# LCDRDY ROMCS (2:3)# CKE UUCAS# ULCAS# MRAS (0:1)# UCAS# LCAS# IOR# IOW# RESET IOCS16# IOCHRDY HOLDRQ# HOLDAK# SRAS# SCAS# BUSRQ (0:1)# BUSAK (0:1)# INTRP IRQ USBINT# PS2INT BUSCLK ARBCLKSEL DP (1:2) DN (1:2) PPON (1:2) OCI (1:2) IEN WAKE After Reset Hi-Z Hi-Z Hi-Z - Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - - - Hi-Z Hi-Z 1 - Hi-Z Hi-Z - 1 0 0 1 0 - - 1 0 0 - - 0 When HOLDAK# = 1 Hi-Z Hi-Z Hi-Z - Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - - - Hi-Z Hi-Z 1 - Hi-Z Hi-Z - Normal operation Normal operation Normal operation Normal operation Normal operation - - Normal operation Normal operation Normal operation - - Normal operation
Remark 0: Low level, 1: High level, Hi-Z: High impedance
Data Sheet U14388EJ2V0DS00
11
PD31172
(2/2)
Signal Name SMI# USBRST# CD (0:7) STROBE# ACK# BUSY PE SELECT AUTOFEED# SELECTIN# ERROR# INIT# DIR1284 RXD CTS# DSR# TXD RTS# DTR# DCD# RI# PS2CLK PS2DATA GPIO (0:23) EXCS (0:5)# LCDBAK CLKOUT48M After Reset 1 - Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 - - - 1 1 1 - - 0 Hi-Z Hi-Z 1 0 1 When HOLDAK# = 1 Normal operation - Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation - - - Normal operation Normal operation Normal operation - - Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation
Remark 0: Low level, 1: High level, Hi-Z: High impedance
12
Data Sheet U14388EJ2V0DS00
PD31172
1.3 External Processing of Pins and Drive Capacity When using the VRC4172, process the pins externally, as shown in the table below. (1/2)
Signal Name SCLK AD (0:24) DATA (0:31) LCDCS# RD# WR# LCDRDY ROMCS (2:3)# CKE UUCAS# ULCAS# MRAS (0:1)# UCAS# LCAS# IOR# IOW# RESET IOCS16# IOCHRDY HOLDRQ# HOLDAK# SRAS# SCAS# BUSRQ (0:1)# BUSAK (0:1)# INTRP IRQ USBINT# PS2INT BUSCLK ARBCLKSEL DP (1:2) DN (1:2) External Processing - - - Pull up Pull up Pull up
Note 1
Drive Capacity 80 pF 80 pF 80 pF - 80 pF 80 pF 40 pF 80 pF 80 pF 80 pF 80 pF 80 pF 80 pF 80 pF - - - 40 pF 40 pF 40 pF - 80 pF 80 pF - 40 pF 40 pF 40 pF 40 pF 40 pF - - Note 2 Note 2
Tolerance 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 5V 5V
Note 1
Pull up Pull up Pull down Pull up Pull up Pull up Pull up Pull up Pull up Pull up - Pull up Pull up - Pull up Pull up Pull up - - - - - - - - - -
Note 1 Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Notes 1. The same specification has been made for these pins in the VR4121. If these pins have been processed in the VR4121, there is no need to perform this processing in the VRC4172. 2. In full-speed mode: 50 pF, In low-speed mode: 350 pF Remark There is no need to perform external processing if no particular external processing has been specified (-).
Data Sheet U14388EJ2V0DS00
13
PD31172
(2/2)
Signal Name PPON (1:2) OCI (1:2) IEN WAKE SMI# USBRST# CD (0:7) STROBE# ACK# BUSY PE SELECT AUTOFEED# SELECTIN# ERROR# INIT# DIR1284 RXD CTS# DSR# TXD RTS# DTR# DCD# RI# PS2CLK PS2DATA GPIO (0:23) EXCS (0:5)# LCDBAK CLKOUT48M External Processing - - - - - - - Pull up Pull up Pull down Pull down Pull down Pull up Pull up Pull up Pull up - - - - - - - - - Pull up Pull up Pull up/pull down - - - Drive Capacity 40 pF - - 40 pF 40 pF - 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF - - - 40 pF 40 pF 40 pF - - 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF Tolerance 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 5V 5V 3V 3V 3V 3V
Remark There is no need to perform external processing if no particular external processing has been specified (-).
14
Data Sheet U14388EJ2V0DS00
PD31172
1.4 Recommended Connection of Unused Pins Connect unused pins as shown in the table below.
Signal Name SCLK AD (0:24) DATA (0:31) LCDCS# RD# WR# LCDRDY ROMCS (2:3)# CKE UUCAS# ULCAS# MRAS (0:1)# UCAS# LCAS# IOR# IOW# RESET IOCS16# IOCHRDY HOLDRQ# HOLDAK# SRAS# SCAS# BUSRQ (0:1)# BUSAK (0:1)# INTRP IRQ USBINT# PS2INT BUSCLK ARBCLKSEL DP (1:2) DN (1:2) Recommended Connection Pull up - - Pull up Pull up Pull up Leave open Pull up Pull down Pull up Pull up Pull up Pull up Pull up - - - - - Leave open Pull up Pull up Pull up Pull up Leave open Leave open Leave open Leave open Leave open Pull up Pull down Pull down Pull down Signal Name PPON (1:2) OCI (1:2) IEN WAKE SMI# USBRST# CD (0:7) STROBE# ACK# BUSY PE SELECT AUTOFEED# SELECTIN# ERROR# INIT# DIR1284 RXD CTS# DSR# TXD RTS# DTR# DCD# RI# PS2CLK PS2DATA GPIO (0:23) EXCS (0:5)# LCDBAK XIN48M XOUT48M CLKOUT48M Recommended Connection Leave open Pull down Pull down Leave open Leave open Pull down Pull down Pull up Pull up Pull down Pull down Pull down Pull up Pull up Pull up Pull up Leave open Pull down Pull up Pull up Leave open Leave open Leave open Pull up Pull up Pull up Pull up Pull down Leave open Leave open Pull up Leave open Leave open
Remark Pins with no particular specification (-) cannot be left unconnected.
Data Sheet U14388EJ2V0DS00
15
PD31172
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Power supply voltage Input voltage Symbol VDD VI VI < VDD + 0.5 V VI < VDD + 3.0 V, DP (2:1), DN (2:1), PS2CLK, PS2DATA pins Output voltage VO VO < VDD + 0.5 V VO < VDD + 3.0 V, DP (2:1), DN (2:1), PS2CLK, PS2DATA pins Operating ambient temperature Storage temperature TA Tstg Conditions Ratings -0.5 to +4.6 -0.5 to +4.6 -0.5 to +6.6 -0.5 to +4.6 -0.5 to +6.6 -40 to +85 -65 to +150 Unit V V V
V V C C
Cautions 1. Do not simultaneously short multiple outputs. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions displayed in DC Characteristics and AC Characteristics in this section indicate the ranges in which normal operation and product quality can be guaranteed. Capacitance (TA = 25C, VDD = 0 V)
Parameter Input capacitance Output capacitance Output capacitance
Note
Symbol CI CO1 CO2
Conditions f = 1 MHz Unmeasured pins returned to 0 V.
MIN.
MAX. 8 8 12
Unit pF pF pF
Note Applicable to DP (2:1), DN (2:1), PS2CLK, and PS2DATA pins.
16
Data Sheet U14388EJ2V0DS00
PD31172
DC Characteristics (TA = -40 to +85C, VDD = 3.3 0.3 V) (1) Pins except for DP (2:1), DN (2:1)
Parameter Output voltage, high Output voltage, low Output voltage, high Output voltage, low
Note 1
Symbol VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VIH1 VIH2 VIL IDD ILI ILIH ILO VI = VDD, GND IOH = -6 mA IOL = 6 mA IOH = -9 mA IOL = 9 mA IOH = -3 mA IOL = 3 mA
Conditions
MIN. 2.4
MAX.
Unit V
0.4 2.4 0.4 2.4 0.4 2.0 2.0 0 VDD 5.5 0.8 300 10 141 10
V V V V V V V V mA
Note 1
Output voltage, high Output voltage, low Input voltage, high Input voltage, high Input voltage, low
Note 2
Note 2
Note 2
Power supply current Input leakage current Input leakage current, high Output leakage current
A A A
VI = VDD, ARBCLKSEL pin VO = VDD, GND
Notes 1. Applicable to SCLK, AD (24:0), DATA (31:0), RD#, WR#, ROMCS (3:2)#, CKE#, UUCAS#, ULCAS#, MRAS (1:0)#, UCAS#, LCAS#, SRAS#, and SCAS# pins. 2. Applicable to PS2CLK and PS2DATA pins. (2) DP (2:1), DN (2:1) pins
Parameter Output voltage, high Output voltage, low Differential input sensitivity Differential common mode range Input voltage, high Input voltage, low Symbol VOH VOL VDI VCM VDI < 200 mV Conditions RL = 15 k (connected to GND) RL = 1.5 k (connected to VDD) 0.2 0.8 2.5 MIN. 2.8 MAX. 3.6 0.3 Unit V V V V
VIH_USB VIL_USB
2.0 0.8
V V
Remark Refer to the USB specification, revision 1.0, for details.
Data Sheet U14388EJ2V0DS00
17
PD31172
AC Characteristics (TA = -40 to +85C, VDD = 3.3 0.3 V) AC test input waveform
VDD All output pins 0V 1.4 V Test points 1.4 V
AC test output test points
VDD All output pins 0V 1.4 V Test points 1.4 V
18
Data Sheet U14388EJ2V0DS00
PD31172
Load Conditions (a) SCLK, AD (0:24), DATA (0:31), RD#, WR#, ROMCS (2:3)#, CLK#, UUCAS#, ULCAS#, ULCAS#, MRAS (0:1)#, UCAS#, LCAS#, SRAS#, SCAS#
SCLK, AD (0:24), DATA (0:31), RD#, WR#, ROMCS (2:3)#, CLK#, UUCAS#, ULCAS#, MRAS (0:1)#, UCAS#, LCAS#, SRAS#, SCAS#
DUT CL = 80 pF
(b) DP (1:2), DN (1:2)
DP (1:2), DN (1:2)
DUT In full-speed mode: CL = 50 pF In low-speed mode: CL = 350 pF
(c) Other output pins
Output pins (except for (a) and (b) above)
DUT CL = 40 pF
Data Sheet U14388EJ2V0DS00
19
PD31172
(1) Clock parameters
Parameter XIN48M clock frequency Symbol fCLK Conditions MIN. TYP. 48.0 MAX. 50.0 Unit MHz
(2) Reset parameters
Parameter RESET signal high-level width USBRST# signal low-level width Symbol tRST tUSBRST Conditions MIN. 30 30 MAX. Unit ns ns
(3) SDRAM interface parameters
Parameter SCLK cycle SCLK high-level width SCLK low-level width Data output hold time Data output delay time Data input setup time Data input hold time Symbol tSCLK tSCLKH tSCLKL tSDM tSDO tSDS tSDH 9.5 2 Conditions MIN. 20.8 8 8 2 15 MAX. Unit ns ns ns ns ns ns ns
tSCLKH SCLK (I/O) AD (24:0), WR#, ROMCS (3:2)#, UUCAS#, ULCAS#, UCAS#, LCAS#, MRAS (1:0)#, SRAS#, SCAS#, CKE (I/O) DATA (31:0) (output) DATA (31:0) (input) Hi-Z tSDM tSDO
tSCLKL
tSCLK
tSDS
tSDH Hi-Z
20
Data Sheet U14388EJ2V0DS00
PD31172
(4) System bus interface parameters (a) Access to I/O area
Parameter Command signal low-level width Address setup time (to command signal) Address hold time (from command signal) IOCS16# valid delay time IOCS16# floating delay time Data output hold time Data output delay time Data input setup time Data input setup time Data input hold time
Note
Symbol tCLCH tAVCL tCHAV tAVCV tAVCZ tDM tDO tDS1 tDS2 tDH
Conditions
MIN. 130 10 10
MAX.
Unit ns ns ns
12 10 6 25 30 10 10 10
ns ns ns ns ns ns ns
Note During 16550-compatible serial communication
AD (24:0) (input) tAVCL IOR#/IOW# (input) tAVCV IOCS16# (output) tDS1 DATA (31:0) (input) tDS2 DATA (31:0) (input)Note tDO DATA (31:0) (output) tDM tDH tDH tCLCH tCHAV
tAVCZ
Note During 16550-compatible serial communication Remark The broken lines indicate high impedance
Data Sheet U14388EJ2V0DS00
21
PD31172
(b) Access to LCD area
Parameter Command signal low-level width Address setup time (to command signal) Address hold time (from command signal) LCDRDY valid delay time LCDRDY set delay time LCDRDY floating delay time Data output hold time Data output delay time Data output valid time Data input setup time Data input hold time Symbol tCLCH tAVCL tCHAV tAVRH tCLRL tAVRZ tDM tDO tDV tDS tDH 10 10 10 6 Conditions MIN. 90 10 10 15 12 10 25 30 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
(i) When accessing the internal PCI bus
AD (24:0) (input) LCDCS# (input) tAVCL RD#/WR# (input) tAVRH LCDRDY (output) DATA (31:0) (input) tDV DATA (31:0) (output) tDM tCLRL tAVRZ tCLCH tCHAV
tDS
tDH
Remark The broken lines indicate high impedance
22
Data Sheet U14388EJ2V0DS00
PD31172
(ii) When accessing the configuration register of the PCI host controller
AD (24:0) (input) LCDCS# (input) tAVCL RD#/WR# (input) LCDRDY (output) Hi-Z tDS DATA (31:0) (input) DATA (31:0) Hi-Z (output) tDO tDM Hi-Z tDH tCLCH tCHAV
Data Sheet U14388EJ2V0DS00
23
PD31172
(5) GPIO parameters
Parameter GPIO (23:0) output delay time GPIO (23:0) interrupt request generation time GPIO (23:0) interrupt request clear time Symbol tGO tGI tGIC Conditions MIN. MAX. 30 30 35 Unit ns ns ns
(a) In output mode
IOW# (input) tGO GPIO (23:0) (output)
(b) In input mode
GPIO (23:0) (input) tGI IRQ (output) (level trigger interrupt) IRQ (output) (edge trigger interrupt) IOW# (input) (edge interrupt request clear) tGIC tGI
24
Data Sheet U14388EJ2V0DS00
PD31172
(6) PCS (Programmable Chip Select) parameters
Parameter EXCS output delay time Symbol tEO Conditions MIN. MAX. 30 Unit ns
AD (24:0) (I/O) tEO EXCS (5:0)# (output) tEO
(7) PWM (Pulse Width Modulation) parameters
Parameter LCDBAK output delay time Symbol tLO Conditions MIN. MAX. 8 tSCLK Unit ns
IOW# (input) tLO LCDBAK (output)Note
Note High level: enable, Low level: disable
Data Sheet U14388EJ2V0DS00
25
PD31172
(8) PS/2 parameters
Parameter PS2CLK clock high-level width PS2CLK clock low-level width PS2CLK output delay time Transmission start time Transmit data output delay time Receive data setup time Receive data hold time Receive disable setup time Symbol tPSCH tPSCL tPSO tPSGO tPSDO tPSDS tPSDH tPSN 0 4T 3T Conditions MIN. 3T 3T T + 20 20 3 T + 20 MAX. Unit ns ns ns ns ns ns ns ns
Remark T = 125 ns (cycle of internal clock for controlling PS/2) (a) Transmission
PS/2 interface disabled IOW# (input)
PS/2 interface enabled
Transmit data setting tPSO tPSO PS2CLK (I/O) Input tPSGO PS2DATA (I/O) Input Start bit Output
tPSCL tPSCH
Input tPSDO DATA0 DATA (1:7), parity bit Stop bit
Output
Input
(b) Reception
tPSCL PS2CLK (I/O) Input tPSDS PS2DATA (I/O) tPSDH Start bit DATA0 DATA (1:7), parity bit
tPSN
Output
Stop bit
26
Data Sheet U14388EJ2V0DS00
PD31172
(9) 16550-compatible serial interface parameters
Parameter Transmit clock division ratio Transmit clock rising edge delay time (from CLK
Note 1
Symbol N ) ) tBHD tBLD tLW
Conditions
MIN. 1
TYP.
MAX. 2 -1
16
Unit
10 15 N=1 N=2 N=3 N>3 0.5CLKC 1CLKC 2CLKC 2CLKC 0.5CLKC 1CLKC 1CLKC (N - 2) CLKC 40 30 10 1 RCLKC Note 2 + 20 30 40 8 BAUC 16 BAUC 24 BAUC + 20 24 BAUC + 20 8 BAUC + 20 30 30 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Transmit clock falling edge delay time (from CLK Transmit clock pulse low-level width
Note 1
Transmit clock pulse high-level width
tHW
N=1 N=2 N=3 N>3
Interrupt cancellation time (from IOR# , when reading LSR register) Interrupt cancellation time (from IOR# , when reading RBR register) Sample clock delay time (from RCLK) Interrupt generation time (from valid data reception, reception error) Interrupt cancellation time (from IOW# , when writing to THR register) Interrupt cancellation time (from IOR# , when reading IIR register) Transmission start time Interrupt generation time (from IOW# , when writing to THR register) Interrupt generation time (from stop bit) RTS#, DTR delay time (from IOW# , when writing to MCR register) Interrupt cancellation time (from IOR# , when reading MSR register) Interrupt cancellation time (from RI# , CTS#, DSR#, DCD#)
tRINT1 tRINT2 tSCD tSINT tHR tIR tIRS tSI tSTI tMDO tRIM tSIM
Notes 1. CLK is the internal system clock of the 16550 serial controller, and has a frequency of 1.8462 MHz. 2. When bit 0 of the FCR register is 1, tSINT = 3 RCLKC + 20 (ns). During a timeout interrupt, tSINT = 8 RCLKC + 20 (ns). Remark CLKC: RCLKC: BAUC: CLK (internal system clock of 16550 serial controller) cycle RCLK (on-chip serial controller receive clock) cycle BAUDOUTB (on-chip serial controller transmit clock) cycle
RCLKC = BAUC in this case.
Data Sheet U14388EJ2V0DS00
27
PD31172
(a) Serial BAUDOUT timing
CLK (internal, 1.8462 MHz) tBLD tBHD BAUDOUTB (1 cycle) (internal) tBLD BAUDOUTB (2 cycles) (internal) tBLD BAUDOUTB (3 cycles) (internal) tBLD BAUDOUTB (N cycles, N > 3) (internal) tBHD tLW tHW tBHD tLW tHW tBHD tLW tHW tHW
tLW
(b) Serial receive timing
RCLK (BAUDOUTB) 8 RCLKC Internal sample clock tSCD 16 RCLKC
RXD (input)
Start bit
DATA (5:8)
Parity bit Stop bit
Internal sample clock tSINT INTRP (output) (receive data existence interruptNote 1) INTRP (output) (receive status interruptNote 2) IOR# (input) (reading RBR register) IOR# (input) (reading LSR register) tRINT1
tRINT2
Notes 1. Dependant on the existence of receive data. At this time, bit 0 of the IER register is 1, and bits 3 to 1 of the IIR register are 0, 1, 0, respectively. 2. Dependant on the receive line status. At this time, bit 2 of the IER register is 1, and bits 3 to 1 of the IIR register are 0, 1, 1, respectively.
28
Data Sheet U14388EJ2V0DS00
PD31172
(c) Serial transmission timing
RXD (input) INTRPNote (output) IOW# (input) (writing to THR register) IOR# (input) (reading IIR register)
Start bit tIRS
DATA (5:8)
Parity bit Stop bit
Start bit tSTI
tHR tSI tHR
tIR
Note Dependant on whether the transmit buffer is empty. At this time, bit 1 of the IER register is 1, and bits 3 to 1 of the IIR register are 0, 0, 1, respectively.
(d) Serial modem control timing
IOW# (input) (writing to MCR register) tMDO RTS#, DTR# (output) tMDO
CTS#, DSR#, DCD# (input) tSIM INTRPNote (output) IOR# (input) (reading MSR register) RI# (input) tRIM tRIM tSIM
tSIM
Note Dependant on the modem status. At this time, bit 3 of the IER register is 1, and bits 3 to 1 of the IIR register are 0, 0, 0, respectively.
Data Sheet U14388EJ2V0DS00
29
PD31172
(10) IEEE1284-compliant parallel interface parameters (a) Parallel port control signal output
Parameter Parallel interface internal clock frequency CD (7:0) output delay time (writing to DATA register) INIT#, STROBE#, AUTOFEED#, SELECTIN# setup time DIR1284 setup time Symbol tCLK1284 t1 t2 t3 Conditions MIN. MAX. 24 30 4T 5T Unit MHz ns ns ns
Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
IOW# (input) t1 CD (7:0) (I/O) INIT#, STROBE#, AUTOFEED#, SELECTIN# (I/O) DIR1284 (output) t2
t3
(b) Compatible mode using FIFO
Parameter CD (7:0) setup time STROBE# pulse width BUSY response time CD (7:0) hold time CD (7:0) hold time
Note 2 Note 1
Symbol t4 t5 t6
Conditions
MIN. 24 T 24 T
MAX.
Unit ns ns
12 T 24 T 0 24 T
ns ns ns ns
(from STROBE# ) (from BUSY )
t7 t8 t9
Note 2
STROBE# setup time
Note 3
Notes 1. When there is no reaction from BUSY at a low level, STROBE# continues to output a low level. 2. Data is held while BUSY is high level. 3. When the FIFO buffer is empty, this signal is held at a high level. Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
CD (7:0) (output) t4 STROBE# (output)
Valid data t5 t7 t8 t6 t9
BUSY (input)
30
Data Sheet U14388EJ2V0DS00
PD31172
(c) During ECP normal-direction transfer
Parameter CD (7:0), AUTOFEED# setup time BUSY response time (from STROBE# ) STROBE# response time BUSY response time (from STROBE# ) CD (7:0) hold time STROBE# setup time
Note
Symbol t10 t11 t12 t13 t14 t15
Conditions
MIN. 1T 0 2T 0 2T 3T
MAX. 2T
Unit ns ns
4T
ns ns
4T 6T
ns ns
Note When the FIFO buffer is empty, this signal is held at a high level. Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
CD (7:0) AUTOFEED# (output) STROBE# (output)
Valid data t10 t14
t11 BUSY (input)
t12
t13
t15
(d) During ECP reverse-direction transfer
Parameter CD (7:0), BUSY setup time AUTOFEED# response time ACK# response time AUTOFEED# response time (from ACK# ) CD (7:0) hold time ACK# setup time
Note
Symbol t16
Conditions
MIN. 0 3T 0
MAX.
Unit ns ns ns
(from ACK# )
t17 t18 t19 t20 t21
5T 0 0
ns ns ns
Note When the FIFO buffer is full, this signal is held at a low level. Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
CD (7:0) BUSY (input) t16 ACK# (input) t17 AUTOFEED# (output)
Valid data
t18
t19
t20
t21
Data Sheet U14388EJ2V0DS00
31
PD31172
(e) Write timing in EPP1.9 mode
Parameter IOCHRDY setup time CD (7:0) output delay time STROBE# setup time, DIR1284 cancellation time (from IOW# ) STROBE# setup time, DIR1284 cancellation time (from BUSY ) SELECTIN#, AUTOFEED# setup time (from STROBE# , valid data output) Timeout generation time SELECTIN#, AUTOFEED# cancellation time (from IOW# ) IOCHRDY cancellation time CD (7:0) hold time STROBE# cancellation time, DIR1284 setup time Symbol t22 t23 t24 Conditions MIN. MAX. 3T 30 5T Unit ns ns ns
t25
4T
ns
t26
0
ns
t27 t28
10 3T
s
ns
t29 t30 t31 1T 1T
4T
ns ns ns
Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
AD (24:0), DATA (31:0) (input) IOW# (input) t22 IOCHRDY (output) t24 STROBE# (output) SELECTIN# AUTOFEED# (output) CD (7:0) (output) t24 DIR1284 (output) t25 BUSY (input) t26
Valid data t27 t29
t31
t28
t23 Valid data
t30
t31
32
Data Sheet U14388EJ2V0DS00
PD31172
(f) Read timing in EPP1.9 mode
Parameter IOCHRDY setup time STROBE# setup time, DIR1284 cancellation time (from IOR# ) STROBE# setup time, DIR1284 cancellation time (from BUSY ) SELECTIN#, AUTOFEED# setup time (from IOR# ) SELECTIN#, AUTOFEED# setup time (from DIR1284 ) Timeout generation time SELECTIN#, AUTOFEED# cancellation time (from IOR# ) CD (7:0) hold time IOCHRDY cancellation time STROBE# cancellation time, DIR1284 setup time Symbol t32 t33 Conditions MIN. MAX. 3T 5T Unit ns ns
t34
4T
ns
t35
6T
ns
t36
30
ns
t37 t38
10 3T
s
ns
t39 t40 t41
0 3T 1T
ns ns ns
Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
AD (24:0) (input) t37 IOR# (input)
DATA (31:0) (output) IOCHRDY (output)
Hi-Z t32
Valid data t40
Hi-Z
t33 STROBE# (output) t34 SELECTIN# AUTOFEED# (output) CD (7:0) (input) t33 DIR1284 (output) BUSY (input) t34 t35 t39 Hi-Z Valid data t36 t38
t41
Hi-Z t41
Data Sheet U14388EJ2V0DS00
33
PD31172
(g) Write timing in EPP1.7 mode
Parameter CD (7:0) output delay time STROBE# setup time SELECTIN#, AUTOFEED# setup time IOCHRDY setup time Timeout generation time IOCHRDY cancellation time SELECTIN#, AUTOFEED# cancellation time STROBE# cancellation time CD (7:0) hold time Symbol t42 t43 t44 t45 t46 t47 t48 t49 t50 1T 30 Conditions MIN. MAX. 30 3T 4T 3T 10 3T 3T Unit ns ns ns ns
s
ns ns ns ns
Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
AD (24:0), DATA (31:0) (input) IOW# (input) t42 CD (7:0) (output) t43 STROBE# (output) t44 SELECTIN# AUTOFEED# (output) DIR1284 (output)
Valid data
t50 Valid data t49
t48
t46 BUSY (input) t45 IOCHRDY (output) t47
34
Data Sheet U14388EJ2V0DS00
PD31172
(h) Read timing in EPP1.7 mode
Parameter DIR1284 setup time SELECTIN#, AUTOFEED# setup time IOCHRDY setup time Timeout generation time IOCHRDY cancellation time SELECTIN#, AUTOFEED# cancellation time CD (7:0) hold time DIR1284 cancellation time Symbol t51 t52 t53 t54 t55 t56 t57 t58 0 1T 30 3T 10 3T 3T Conditions MIN. MAX. 3T Unit ns ns ns
s
ns ns ns ns
Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
AD (24:0) (input) IOR# (input) DATA (31:0) (output) STROBE# (output) t52 SELECTIN# AUTOFEED# (output) CD (7:0) (input) DIR1284 (output) t54 BUSY (input) t53 IOCHRDY (output) t55 Hi-Z t51 Valid data t58 t56 Hi-Z Hi-Z
Valid data
t57 Hi-Z
Data Sheet U14388EJ2V0DS00
35
PD31172
(i) Interrupt request timing
Parameter Interrupt request setup time Interrupt request generation time (from ACK#, ERROR# ) Interrupt request cancellation time (from IOW# ) Interrupt request cancellation time
Note
Symbol t59 t60
Conditions
MIN. 4T
MAX.
Unit ns
3T
ns
t61 t62 t63
5T 3T 5T
ns ns ns
(from IOR# )
Interrupt request generation time (from IOW# )
Note When bit 7 of the CNFGA register = 0 Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
IOW# (input) IOR# (input) ACK# (input) t60 INTRP, IRQ (output) t59 ERROR# (input) t60 t60 t61 t60 t62 t63
36
Data Sheet U14388EJ2V0DS00
PD31172
(11) USB interface Applicable to the DP (2:1) and DN (2:1) pins. Refer to the USB specification, revision 1.0, for details.
Parameter Full-speed mode Rise time Fall time tR, tF matching Differential output signal crossover point Low-speed mode Rise time Symbol tR tF tRFM VCRS Conditions CL = 50 pF CL = 50 pF tR/tF MIN. 4 4 90 1.3 MAX. 20 20 110 2.0 Unit ns ns % V
tR
CL = 50 pF CL = 350 pF
75 300 75 300 80 1.3 120 2.0
ns ns ns ns % V
Fall time
tF
CL = 50 pF CL = 350 pF
tR, tF matching Differential output signal crossover point Impedance
tRFM VCRS
tR/tF
Imp.
28
43
90% DP (2:1), DN (2:1) 10% tR
90% VCRS 10% tF
Data Sheet U14388EJ2V0DS00
37
PD31172
3. PACKAGE DRAWING
208-PIN PLASTIC FBGA (15x15) OUTLINE DRAWINGS
D D1
w
SB ZD B 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 UTRPN MLK JH GF EDCB A
ZE
A E1 E
INDEX MARK 4 - R0.3 4 - C1.0
w
SA
A 25 y1 S A2 S
y
S 208 - b
e
A1
x
M
SAB
ITEM D D1 E E1 w e A A1 A2 b x y y1 ZD ZE MILLIMETERS 15.000.10 14.4 15.000.10 14.4 0.20 0.80 1.510.15 0.350.10 1.16 0.50 +0.05 -0.10 0.08 0.10 0.20 1.1 1.1 P208S1-80-2C
38
Data Sheet U14388EJ2V0DS00
PD31172
4. RECOMMENDED SOLDERING CONDITIONS
The PD31172 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 4-1. Surface Mounting Type Soldering Conditions
Soldering Method
Soldering Conditions
Recommended Condition Symbol IR35-107-3
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Note Count: Three times or less, Exposure limit: 7 days (after that, prebake at 125C for 10 to 72 hours)
VPS
Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Note Count: Three times or less, Exposure limit: 7 days (after that, prebake at 125C for 10 to 72 hours)
VP15-107-3
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U14388EJ2V0DS00
39
PD31172
[MEMO]
40
Data Sheet U14388EJ2V0DS00
PD31172
[MEMO]
Data Sheet U14388EJ2V0DS00
41
PD31172
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
42
Data Sheet U14388EJ2V0DS00
PD31172
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U14388EJ2V0DS00
43
PD31172
Related Documents:
VRC4172 User's Manual (U14386E) VR4121 User's Manual (U13569E) VR4121 Data Sheet (U14691E) Electrical Characteristics for Microcomputer (IEI-601) However, preliminary
Reference Materials:
The related documents indicated in this publication may include preliminary versions. versions are not marked as such.
VR4121 and VRC4172 are trademarks of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

▲Up To Search▲

Price & Availability of UPD31172

	To Download UPD31172 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .